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Bits to Light: How an Optical Transceiver Sends Data

The path a bit takes through an optical link, from the host's SerDes through FEC, the modulation format, the driver and the laser or modulator, the fiber, the photodiode and transimpedance amplifier, to clock recovery and decoding, with the numbers for a 100 Gb/s PAM4 lane: 53.125 GBd, 18.8 ps symbols, the RS(544,514) FEC and the 9.5 dB PAM4 penalty.

Published October 5, 20265 min read

Scope

This article follows data through a short-reach optical link of the kind used inside data centers, from the electrical bits leaving a switch chip to the bits recovered at the far end. It names each block, says what it does to the signal, and gives the numbers for one common case: a single 100 Gb/s lane using four-level pulse amplitude modulation (PAM4), the building block of 400G and 800G pluggable modules. Long-haul coherent links follow the same outline with a far more complex modulation and coherent DSP.

In short: the host sends bits over an electrical SerDes lane; the module adds error-correction parity, maps pairs of bits onto four amplitude levels, and drives a laser or modulator so that the light's power follows those levels; at the receiver a photodiode turns power back into current, a transimpedance amplifier into voltage, and a DSP recovers the clock, decides each symbol, and corrects the errors.

The chain

BlockInputOutputMain parameter
Host SerDesParallel data in the switchSerial electrical laneLane rate
FEC encoderData bitsData plus parityOverhead, correctable error rate
Modulation (DSP)BitsSymbols on 2 or 4 levelsSymbol rate
DriverLow-voltage symbolsDrive voltage or currentSwing, bandwidth
Laser or modulatorDrive signalModulated lightExtinction ratio, bandwidth
FiberLightAttenuated, dispersed lightLoss, dispersion
PhotodiodeLightPhotocurrentResponsivity, bandwidth
TIACurrentVoltageGain, noise
DSP and CDRSampled voltageBits, clockEqualization, decision thresholds
FEC decoderBits with errorsCorrected bitsPre-FEC BER limit

Line rate and error correction

A 100 Gb/s Ethernet lane does not put exactly 100 Gb/s on the fiber. The data is first encoded in blocks (transcoded to 256b/257b), then protected by a Reed-Solomon forward error correction code, RS(544,514), which adds 30 parity symbols to every 514 data symbols, an overhead of 5.8%. The line rate becomes

100 Gb/s×257256×544514  =  106.25 Gb/s.100\ \text{Gb/s} \times \frac{257}{256} \times \frac{544}{514} \;=\; 106.25\ \text{Gb/s}.

The FEC lets the link run with errors before correction: this code is designed to deliver an essentially error-free output when the bit error rate before correction is below about 2.4 × 10⁻⁴. That pre-FEC threshold, not error-free transmission, is what the optics are designed and tested against.

Modulation: NRZ and PAM4

NRZ sends one bit per symbol on two levels; PAM4 sends two bits per symbol on four levels, halving the symbol rate for the same bit rate. The 106.25 Gb/s lane above runs at 53.125 GBd in PAM4, so each symbol lasts 1/(53.125 GHz) = 18.8 ps. For comparison, a 25 Gb/s NRZ lane runs at 25.78125 GBd, 38.8 ps per symbol.

The cost of PAM4 is in signal-to-noise ratio. Its three eyes share the same total swing that NRZ uses for one, so each is a third as tall: a penalty of 20log⁡10320\log_{10}3 = 9.5 dB in electrical SNR for the same peak-to-peak signal, before any other impairment. PAM4 also needs the levels to be evenly spaced, which makes the transmitter's linearity and the receiver's equalization matter. The trade is worth it because doubling the symbol rate instead would need twice the bandwidth from every electrical and optical component. Other formats are covered in modulation formats.

Turning symbols into light

There are two ways to modulate the light:

  • Direct modulation. The drive current of a DFB laser or VCSEL is varied, so its output power follows the symbols. Simple and low-power; limited in speed by the laser's dynamics and accompanied by frequency chirp, which limits reach in dispersive fiber. VCSELs over multimode fiber are the usual choice for the shortest reaches.
  • External modulation. The laser runs continuously and a modulator varies the light: an electro-absorption modulator integrated with the laser, or a Mach-Zehnder or microring modulator, often in silicon photonics. Faster and with less chirp, at the cost of a modulator and its driver.

The driver amplifies the DSP's output to the voltage or current the device needs. Its bandwidth and linearity, and the modulator's, decide how open the PAM4 eyes are at the transmitter, measured as TDECQ (see TDECQ Measurement).

Through the fiber

The fiber attenuates the signal, and dispersion spreads each symbol in time. For a few hundred meters to a few kilometers of single-mode fiber near 1310 nm, where dispersion is small, loss is dominated by connectors; over multimode fiber, modal dispersion limits the reach. Wavelength-division multiplexing puts several lanes on one fiber; parallel fibers are the other option. How these choices appear in product names is explained in How to Read Transceiver Names, and the power arithmetic in the link budget calculator.

Turning light back into bits

A photodiode converts the optical power into a current. At a received average power of −5 dBm (0.32 mW) and a responsivity of 0.8 A/W, the average photocurrent is 253 μA. The transimpedance amplifier converts the current to a voltage with low added noise; its noise and the photodiode's together set the receiver sensitivity, the lowest power at which the pre-FEC error rate stays below the threshold.

The DSP then samples the signal, equalizes it to undo the bandwidth limits of the whole chain, recovers the symbol clock from the data itself (there is no separate clock line), and decides which of the four levels each symbol is closest to. The FEC decoder corrects the remaining errors, and the bits are sent to the host over another SerDes lane. Modules whose electrical and optical rates are equal sometimes omit the DSP and use only analog equalization and a retimer, or none at all, to save power.

Where the power goes

In a pluggable module, the DSP and its SerDes interfaces account for a large share of the power, the laser and driver much of the rest. That is the motivation for co-packaged optics, which places the optics beside the switch chip so that the long electrical lanes, and the circuitry that drives them, are shortened or removed.

References: IEEE Std 802.3-2022, IEEE Standard for Ethernet (clauses 91 and 119 for RS-FEC; clause 140 for 100GBASE-DR); G. P. Agrawal, Fiber-Optic Communication Systems (5th ed., Wiley, 2021).