SerDes (serializer and deserializer)
The high-speed electrical transceiver at the edge of a switch, processor or DSP chip that turns parallel data into a single fast serial lane and back, with the equalization and clock recovery needed to push it through a lossy board channel.
Inside a chip, data moves on wide parallel buses at modest clock rates. Between chips, pins and board traces are scarce, so the data is serialized: a SerDes takes a parallel word, sends it as one fast serial stream on a differential pair, and the SerDes at the other end recovers the clock from the data itself and deserializes it. Every port of a datacenter switch, and every electrical lane between a switch and its optics, is one SerDes lane, and a modern switch chip carries hundreds of them.
The transmitter and receiver are mostly equalizers. A board trace or cable attenuates high frequencies more than low ones, which smears each symbol into its neighbors. The transmitter pre-distorts the signal with a feed-forward equalizer (FFE), a few taps that subtract scaled copies of adjacent symbols; the receiver applies a continuous-time linear equalizer (CTLE) that boosts the high frequencies back, then in modern designs digitizes the signal with an ADC and applies a longer digital FFE and a decision-feedback equalizer (DFE) that cancels the trailing interference of symbols already decided. Clock and data recovery locks a sampling clock to the incoming transitions. The quality of the result is judged on the eye diagram and ultimately the bit error rate before FEC.
Lane rates advance in generations, each named by its approximate bit rate. The 112G generation signals PAM4 at about 53 GBd; the 224G generation, which carries the 200G-per-lane Ethernet interfaces, signals PAM4 at about 106 to 113 GBd, a unit interval of 9.41 ps at 106.25 GBd. Each doubling of the symbol rate doubles the Nyquist frequency, and a trace's loss in dB grows roughly in proportion to frequency, which is why the reach of a copper lane shrinks with each generation and why the SerDes's share of chip power grows.
SerDes performance sets the boundaries between the optical interconnect architectures. A conventional pluggable module contains its own retiming DSP, which terminates the host SerDes's link at the module edge and launches a clean optical signal. In linear pluggable optics that DSP is removed and the host SerDes must equalize the complete electrical and optical channel end to end, so the SerDes's equalization reach decides whether the link closes; LRO keeps the transmit retimer and relies on the host only on receive. Co-packaged optics shorten the electrical channel to millimeters and allow a simpler, lower-power SerDes. The trade is set out in Pluggable, LRO, LPO, CPO.
References: IEEE Std 802.3ck-2022 (100 Gb/s per lane electrical interfaces); OIF, Common Electrical I/O (CEI) 112G implementation agreements; IEEE P802.3dj (200 Gb/s per lane).