PAM4
Four-level pulse amplitude modulation, encoding 2 bits per symbol. The dominant modulation format for 50G+/lane data center optical interconnect, doubling bit rate per Hz of optical bandwidth vs NRZ.
PAM4 (pulse amplitude modulation, 4 levels) is a 2-bit-per-symbol modulation format that has been the dominant short-reach optical interconnect modulation since the late 2010s. Compared to traditional NRZ binary signaling, PAM4 doubles the bit rate for the same baud rate (symbol rate), at the cost of reduced noise margin.
Operating principle. Each transmitted symbol takes one of four optical power levels, encoding two bits:
| Symbol level | Gray-coded bits (typical) |
|---|---|
| Level 0 (lowest) | 00 |
| Level 1 | 01 |
| Level 2 | 11 |
| Level 3 (highest) | 10 |
The use of Gray coding (adjacent levels differ by one bit) means most decision errors flip only one bit per symbol, improving BER after error correction.
Bit rate vs baud rate. PAM4 carries 2 bits per symbol; at the same baud rate as NRZ, it carries twice the bit rate. Standard PAM4 deployments:
| Standard | Baud rate | Bit rate per lane | Bit rate × N lanes |
|---|---|---|---|
| 100GBASE-DR / FR1 | 53.125 Gbaud | 106.25 Gb/s | 1 lane = 106.25G |
| 200GBASE-DR4 / FR4 | 26.5625 Gbaud | 53.125 Gb/s | 4 lanes = 212.5G |
| 400GBASE-DR4 / FR4 | 53.125 Gbaud | 106.25 Gb/s | 4 lanes = 425G |
| 800GBASE-DR8 | 53.125 Gbaud | 106.25 Gb/s | 8 lanes = 850G |
The 26.5625 and 53.125 Gbaud symbol rates include the FEC overhead; the nominal lane rates (50G, 100G) refer to the payload.
Why PAM4 displaced NRZ. At baud rates above 25 Gbaud, electronic transceivers face increasingly severe challenges:
- Channel bandwidth (cables, PCB traces, packaging)
- Eye-diagram opening reduces with bandwidth
- SerDes signal integrity becomes harder
- Power consumption per Gb/s scales superlinearly
PAM4 allows the same bit rate at half the baud rate, halving the bandwidth requirement at modest signal-integrity cost. The same 25 Gbaud SerDes that supported 25G NRZ in 100G-SR4 now supports 50G PAM4 in 200G-SR4.
Power penalty vs NRZ. Compared to NRZ at the same average optical power:
- Eye amplitude: each of the three eyes spans 1/3 of the full swing, where NRZ's single eye spans all of it
- Electrical SNR penalty per eye: dB, since each eye has 1/3 of the amplitude
- Optical power penalty: dB at the same average optical power, for thermal-noise-limited detection
This penalty is why PAM4 requires substantial forward error correction (FEC), typically the RS(544,514) "KP4" code, with about 6% overhead.
Simulated PAM4 eye over two symbol periods. At the sampling instant the traces gather at the four levels, spaced a third of the full swing apart, and the three openings between them (amber) are the eyes.
Modulator requirements. PAM4 places stricter demands on the optical modulator:
- Linearity: the modulator must produce equally-spaced levels; nonlinearity (e.g., Mach-Zehnder cosine response) requires pre-distortion or DSP compensation
- Extinction ratio: kept moderate so that all four levels stay on the linear part of the transfer curve; 400GBASE-DR4 specifies a minimum of 3.5 dB
- Eye height and OMA: PAM4 transmit and receive limits are written in outer OMA, the swing between the outer levels, and each eye is one third of it; average power follows from the OMA and the extinction ratio
- Drive voltage swing: must drive the modulator linearly across 4 levels
Standard PAM4 modulators in deployment:
| Modulator type | Bandwidth | Use | |
|---|---|---|---|
| Silicon photonic MZ (depletion) | 30 – 50 GHz | 1 – 3 V·cm | 100/200G PAM4 |
| InP-based MZ | 40 – 60 GHz | 1 – 2 V·cm | 400/800G PAM4 |
| Lithium niobate on insulator (LNOI) | 70 – 110 GHz | 1.5 – 3 V·cm | 800G+ PAM4 |
| Electro-absorption modulator (EAM) | 40 – 60 GHz | nonlinear; needs pre-distortion | 100/200G PAM4 |
Receiver requirements. PAM4 receivers need 3 decision levels (vs 1 for NRZ) and tighter linearity:
- Linear TIA: must amplify all 4 levels equally
- High-speed ADC: typically one sample per symbol, about 53 GSa/s for a 100 Gb/s lane and twice that for 200 Gb/s
- DSP: feedforward equalization, decision-feedback equalization
- Clock recovery: more complex than NRZ due to 4-level transitions
Modern PAM4 modules pair a SiGe or CMOS TIA with a CMOS DSP chip, in 7 nm, 5 nm or newer processes, that holds the ADC and the equalizers.
FEC requirements. PAM4 systems require FEC to recover from the worse pre-FEC BER:
| Standard | Lane rate | FEC | Pre-FEC BER threshold |
|---|---|---|---|
| 100GBASE-DR, 400GBASE-DR4 | 100 Gb/s | RS(544,514) "KP4" | |
| 800GBASE-DR8 | 100 Gb/s | RS(544,514) | |
| 800GBASE-DR4, 1.6TBASE-DR8 (IEEE 802.3dj, 500 m) | 200 Gb/s | RS(544,514), at 106.25 GBd | |
| 800GBASE-DR4-2 (IEEE 802.3dj, 2 km) | 200 Gb/s | RS(544,514) with an inner Hamming(128,120) code, at 113.4375 GBd | Higher, set by the inner code |
The pre-FEC BER threshold ( for KP4) is far higher than NRZ's classical . It is set by the FEC's correction capability, so that the corrected output meets the Ethernet target at the MAC, a BER of for 400GbE.
Eye diagram. PAM4 eye diagrams have three eyes vertically (between Levels 0/1, 1/2, 2/3) and one horizontally per symbol. Standard measurements:
- Middle eye height: opening of the eye between levels 1 and 2
- Outer eye heights: openings of the upper and lower eyes
- Eye linearity: uniformity of the three eye heights
- Skew: lane-to-lane timing skew
PAM4 eye diagrams are noticeably "noisier" than NRZ even with perfect signals. The 3-level discrimination is inherently less robust.
Optical interconnect generations. PAM4 optics have advanced by lane rate:
- 50 Gb/s lanes (26.5625 Gbaud): 200G modules such as 200GBASE-DR4 and 200GBASE-SR4
- 100 Gb/s lanes (53.125 Gbaud): 100GBASE-DR, 400GBASE-DR4 and FR4, 800GBASE-DR8
- 200 Gb/s lanes (IEEE 802.3dj): 800GBASE-DR4 and 1.6TBASE-DR8
- 400 Gb/s lanes: under study, with PAM4 at higher symbol rates, PAM6 and coherent-lite formats among the candidates
PAM4 vs coherent. PAM4 is "direct detection": single photodiode per lane, no local oscillator. Coherent uses LO + balanced detection + DSP, supporting higher spectral efficiency (DP-QPSK = 4 bits/symbol; DP-16QAM = 8 bits/symbol) but with higher cost and power. For short reach (under 10 km), PAM4 is preferred for cost; for long reach (> 80 km), coherent is necessary.
Beyond PAM4. Future directions:
- PAM6 / PAM8: and 3 bits per symbol; higher capacity at greater SNR cost
- Probabilistic shaping: non-uniform symbol probabilities to optimize for noise
- Multidimensional codes: jointly encode bits across multiple symbols
- Coherent at shorter reach: 400ZR and 800ZR for data center interconnect, and the OIF's 800LR for campus-reach links
Transmitter conformance for PAM4 lanes is scored by TDECQ; the measurement procedure is Measuring TDECQ on a PAM4 transmitter, and the PAM4 Eye & TDECQ Explorer computes it live from a synthesized eye.
How this fits into the full path from host bits to light and back, with the 100G lane arithmetic, is traced in Bits to Light.
References: Saleh & Teich, Fundamentals of Photonics (3rd ed., Wiley, 2019); IEEE 802.3bs, 802.3cd, 802.3df and 802.3dj for the PAM4 PHY specifications; OIF (Optical Internetworking Forum) CEI-56G and CEI-112G specifications; Agrawal, Fiber-Optic Communication Systems (4th ed., 2010) for the underlying modulation theory.