Retimer (clock and data recovery)
A circuit that recovers the clock from an incoming high-speed signal, decides each symbol, and retransmits a clean, re-timed copy, resetting the jitter and noise budget. Distinguished from a redriver, which only amplifies and equalizes.
A high-speed electrical or optical lane degrades as it travels: loss and dispersion close the eye, noise adds to every level, and jitter accumulates. A retimer stops the accumulation. It equalizes the incoming signal, recovers a clock from its transitions with a clock and data recovery (CDR) loop, decides the value of each symbol, and sends the decided symbols out again on a fresh transmitter. What leaves the retimer is a new signal with its own clean edges and full eye opening; the link is split into two segments, each with its own loss and noise budget. A redriver, by contrast, is a linear amplifier and equalizer that makes no decisions, so noise and jitter from the first segment pass straight through to the second.
A retimer removes only the jitter its CDR does not follow. The CDR tracks slow phase wander below its loop bandwidth and passes it through, so that the retimer's clock stays locked to the data, and it rejects faster jitter above the bandwidth. Standards therefore specify jitter transfer, the gain from input to output jitter against frequency, as part of a retimer's behavior. The retimer also adds latency, from its equalizer, CDR and any buffering, and power, which grow with the lane rate.
In pluggable optical modules, the retimer is the DSP. A conventional pluggable retimes in both directions: host electrical lanes are recovered and re-driven onto the optics, and the received optical signal is equalized, decided and sent to the host as a new electrical signal, which is what lets any compliant host work with any compliant module. At 100 and 200 Gb/s per lane the DSP is a large share of the module's power, and the alternatives remove part of it: LRO keeps retiming on the transmit path only, and linear pluggable optics remove it altogether, relying on the host SerDes to equalize the whole path from end to end. The same trade appears on boards and in cables, where retimers extend copper reach between switch and module and active electrical cables embed one in each connector.
The comparison between the retimed, half-retimed and linear designs, with their power figures, is in Pluggable, LRO, LPO, CPO.
References: IEEE Std 802.3ck-2022; OIF, Common Electrical I/O (CEI) 112G implementation agreement.