Silicon Photonics Foundries, PDKs and MPW Runs: How a Shuttle Works
How a photonic chip gets made in a shared foundry run: what a process design kit provides, how a multi-project wafer (MPW) shuttle is organized, the steps from design to tape-out to delivered dies, what to put on a first chip, and the common reasons first silicon disappoints.
Scope
This article explains how a photonic integrated circuit is designed for and fabricated in a commercial or research foundry through a multi-project wafer (MPW) run, the usual route for universities, start-ups and prototype work. It describes the process rather than particular foundries, whose platforms, prices and schedules change and should be taken from their current documentation.
In short: the foundry publishes a process design kit (PDK) describing its process, rules and characterized components; designers lay out their chips against it and submit the layout by a fixed deadline; the foundry combines many customers' designs on shared reticles, fabricates the wafers, dices them and ships each customer their dies, typically months later. Sharing the masks and wafers divides a cost that would otherwise be prohibitive for a small number of chips.
Why shuttles exist
A full set of photomasks for a photonics process, and a dedicated lot of wafers, cost far more than a research group or a start-up can spend on a design that may need several iterations. An MPW run puts many designs side by side in one reticle field, so that each customer pays for an area of the field rather than for the whole mask set. The scanner field of a deep-ultraviolet lithography tool is about 26 × 33 mm; divided into 5 × 5 mm dies it holds 30 of them, each potentially a different customer's design. The trade is less control: the process, the layer stack and the schedule are fixed, and the number of dies each customer receives is limited.
What the PDK provides
| Part | Contents | Used for |
|---|---|---|
| Process description | Layer stack: silicon thickness (often 220 nm on silicon-on-insulator), etch depths, nitride, doping, germanium, metals, heaters | Choosing waveguide geometries and simulating custom devices |
| Design rules | Minimum widths, gaps, overlaps, enclosures, densities | Design-rule checking before submission |
| Component library | Waveguides, bends, grating and edge couplers, splitters, phase shifters, modulators, germanium photodetectors | Building circuits from characterized parts |
| Compact models | S-parameters or behavioral models of library components | Circuit simulation before tape-out |
| Test and packaging rules | Coupler positions, pad pitches, keep-out zones | Probing and packaging the dies |
Library components are measured on the foundry's wafers, so their models describe what the process actually produces, including variation from wafer to wafer. Custom components outside the library are allowed but carry the designer's own risk; they must still satisfy the design rules.
From design to dies
- Choose the platform. Silicon, silicon nitride or another platform, set by the wavelength band, loss, power handling and active components needed.
- Reserve area. Register for a run before its deadline and choose a die size; area is usually sold in fixed blocks.
- Design. Simulate custom components (see Choosing a Photonics Simulation Method), assemble the circuit from library cells and custom cells, and simulate it at circuit level with the compact models.
- Lay out and verify. Produce the layout (usually GDSII or OASIS files) inside the die boundary, run the foundry's design-rule check until it is clean, and check that every optical and electrical connection is what was intended.
- Tape out. Submit the layout by the deadline. Most foundries run their own checks and return violations for correction.
- Fabrication. The foundry merges all designs into the reticle and processes the wafers. This is the long step, usually months.
- Delivery. Wafers are diced and each customer receives their dies, sometimes with optional services such as wafer-level test, packaging or fiber attachment.
Planning a first chip
The first run of a new design is mostly about learning what the process gives. Space spent on test structures usually pays back more than space spent on a larger circuit:
- Loss structures: waveguides of several lengths for cutback loss of each waveguide type used.
- Coupler calibration: back-to-back coupler pairs, so that the coupling loss can be de-embedded from device measurements.
- Parameter sweeps: each custom device repeated with its critical dimension stepped above and below nominal, since fabricated widths differ from drawn widths.
- Resonators: ring resonators to measure effective and group index and loss precisely (see ring resonator Q extraction).
- Duplicates: two or more copies of anything important, in case of a defect or a broken coupler.
Plan the measurement before the layout: coupler pitch and orientation matching the fiber array or probe station that will be used, electrical pads matching the probe cards, and labels readable under the microscope.
Why first silicon disappoints
Width and thickness variation. Silicon waveguide effective index changes noticeably with nanometer-scale width and thickness changes, shifting the resonances of rings and the splitting of couplers. Designs that tolerate variation, or include tuning, survive it; sweeps show how much there is.
Custom components outside the library. Devices designed from simulation alone often differ from what the process produces; this is the reason for sweeps and duplicates.
Rule-clean but wrong. A design can pass every rule and still have a disconnected waveguide, a swapped port or a coupler facing the wrong way. Visual checks and connectivity checks catch these.
Measurement mismatch. Couplers at the wrong pitch, pads too small for the probes, or a layout that cannot be reached with the available setup can make good devices unmeasurable.
The full design flow that leads up to a shuttle submission is mapped in The Silicon Photonics Design Flow.
References: L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University Press, 2015); W. Bogaerts and L. Chrostowski, "Silicon photonics circuit design: methods, tools and challenges," Laser and Photonics Reviews 12, 1700237 (2018).