The Silicon Photonics Design Flow: From Mode Solver to Tape-Out

Scope

This article lays out the whole design flow for a photonic integrated circuit on a silicon platform, from the waveguide cross-section to the measured chip, and points to the site's detailed pages for each step. It is a map rather than a manual: each section says what the step decides, which tool or method does it, and what commonly goes wrong.

In short: choose a platform and waveguide with a mode solver; design or select each component, simulating custom ones with EME or FDTD; assemble the circuit from compact models and simulate it; make the design tolerant of fabrication variation and temperature; lay it out against the foundry's rules and verify it; tape out; and measure first silicon with test structures planned from the start.

The steps

1. Platform

Silicon on insulator, usually with a 220 nm silicon layer, gives strong confinement, small bends, carrier-based modulators and germanium detectors, and suits the telecom bands. Silicon nitride gives lower loss, wider transparency and lower thermal sensitivity, without the active devices. The choice is usually made by the wavelength, the loss budget and which active components the circuit needs, and then by which foundries offer the platform. How shared foundry runs work is described in Silicon Photonics Foundries, PDKs and MPW Runs.

2. Waveguide

A mode solver on the waveguide cross-section gives the effective and group index, the number of guided modes and the field shape. These set the single-mode width, the minimum bend radius, the spacing at which neighboring waveguides couple, and the index used everywhere downstream. The site's Waveguide Mode Explorer solves the slab case exactly.

3. Components

Library components from the foundry's process design kit come with measured models and should be used wherever they fit. Custom components are simulated with the method that suits their geometry: eigenmode expansion for long, slowly varying devices such as tapers and MMIs, FDTD for grating couplers and anything that scatters or resonates. Choosing a Photonics Simulation Method compares the methods; the site's directional coupler and MZI and ring resonator tools cover common building blocks.

4. Circuit

Each component is reduced to a compact model, its S-parameters against wavelength, and a circuit simulator joins them with waveguide sections. This predicts the spectrum of a filter, the transfer function of an interferometer or the response of a whole transceiver in seconds, which makes it practical to sweep design choices.

5. Robustness: variation and temperature

Fabricated widths and thicknesses differ from the drawn values by nanometers, and in tightly confining silicon waveguides that is enough to move resonances and change splitting ratios. Temperature does the same: a silicon strip ring near 1550 nm shifts by about 67 pm/K (see Ring Resonator Thermal Tuning and Locking).

Worked example. A silicon ring of 10 μm radius has a free spectral range of 8.9 nm. Reaching an arbitrary target wavelength may need a shift of up to one FSR, which at 67 pm/K is 133 K of heating, the reason ring-based circuits budget heater power or use larger rings and wider-band designs. A design that works only at nominal dimensions and temperature rarely works on the chip; corner and Monte Carlo runs over the PDK's variation data show how much margin or tuning is needed.

6. Layout and verification

The layout turns the circuit into mask geometry: waveguides routed between components, bends at or above the minimum radius, heaters and metal routing, pads, and the couplers that will connect the chip to fibers. Verification has two parts. The design-rule check confirms that every shape meets the foundry's rules. Connectivity checks confirm that the layout matches the intended circuit, which for photonics also means that waveguides meet at matching widths and angles and that no unintended crossing or gap exists. Both should be clean before submission.

7. Tape-out and fabrication

The verified layout is submitted to the foundry by the run's deadline. For prototypes this is usually a multi-project wafer run shared with other designs; fabrication typically takes months.

8. Test

First silicon is measured on a probe station or after packaging. Test structures planned into the layout make the results interpretable: cutback structures for waveguide loss, back-to-back couplers for coupler loss de-embedding, and rings for index and loss (ring resonator Q extraction). Coupling light in is covered in Fiber-to-Chip Coupling and first-light grating coupler alignment, and testing at scale in Wafer-Level Optical Testing. The measurements feed back into the models for the next iteration.

Common errors

Designing at nominal only. Simulate across the foundry's variation and the operating temperature range, and include tuning where the margin is too small.

Custom cells without sweeps. Lay out each custom device with its critical dimension stepped above and below nominal, so that the measured optimum can be found.

Layout not matched to the test setup. Coupler pitch, orientation and pad positions must suit the fiber arrays and probes that will be used.

No calibration structures. Without loss and coupler structures on the same chip, device measurements cannot be separated from the losses around them.

References: L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University Press, 2015); W. Bogaerts and L. Chrostowski, "Silicon photonics circuit design: methods, tools and challenges," Laser and Photonics Reviews 12, 1700237 (2018).