Silicon-on-insulator (SOI)

Silicon-on-insulator is a layered wafer: a silicon device layer (most commonly 220 nm for photonics), a buried oxide (BOX) of 2–3 µm, and a thick silicon handle. Waveguides are etched into the device layer; the BOX isolates the mode from the handle below, and oxide or air cladding completes the confinement.

The platform's defining number is index contrast: silicon at $n \approx 3.48$ against oxide at $n \approx 1.44$. That contrast confines the mode to ~0.1 µm² areas, permits bend radii of a few microns, and therefore allows dense circuits (thousands of components per die) fabricated with the lithography, etching, and process control of CMOS foundries. This manufacturing inheritance, more than any optical property, is why silicon photonics dominates datacom transceivers.

The same tight confinement sets the platform's costs. Sidewall roughness scatters strongly against a high-contrast wall (typical strip-waveguide loss ~1–2 dB/cm; rib geometries lower). Sub-micron dimensions make device response sensitive to nanometer fabrication variation, and silicon's strong thermo-optic coefficient makes everything a thermometer. At telecom wavelengths silicon is transparent linearly but suffers two-photon absorption at high intensity, with the generated free carriers absorbing further. This sets the practical ceiling on optical power in silicon waveguides.

Two structural gaps define the ecosystem around SOI. Silicon's indirect bandgap yields no practical laser, so light sources are attached: flip-chip bonded, heterogeneously bonded III-V, or external. And silicon's centrosymmetry provides no Pockels effect, so fast modulation uses the plasma dispersion effect in p-n junctions, with germanium grown on silicon serving as the photodetector.

Standard foundry menu on 220 nm SOI: strip and rib waveguides, grating and edge couplers, carrier-depletion Mach–Zehnder and ring modulators, Ge photodiodes, thermo-optic phase shifters.