Heterogeneous integration
The combination of multiple optical material systems on a single chip, typically by bonding or transfer-printing dissimilar materials onto a common substrate. The standard architecture for combining silicon photonic passives with III-V lasers.
Heterogeneous integration is the combination of two or more distinct material systems on a single photonic integrated circuit, using bonding, transfer-printing, or selective epitaxial growth to assemble materials that cannot share a single epi growth process. The most common variant in photonics is III–V on silicon: bonding small InP or GaAs dies onto a CMOS-fabricated silicon photonic wafer to add active functions (lasers, semiconductor optical amplifiers, modulators) that silicon cannot perform natively.
Why heterogeneous integration matters. Silicon photonics is unmatched for passive structures (waveguides, modulators, photodetectors via Ge-on-Si). But silicon has an indirect bandgap — it cannot lase efficiently at room temperature. Adding lasers to silicon photonic systems requires either:
- External laser modules with fiber I/O to the silicon PIC (high cost, packaging-dominated)
- Heterogeneous integration of III–V lasers on the silicon chip itself (low cost at scale, lower packaging burden)
The latter approach is the path being pursued by all major silicon photonic foundries and integrated device manufacturers (Intel, Cisco/Acacia, IMEC, AIM Photonics).
Standard integration techniques.
| Technique | Description | Maturity | Bond quality |
|---|---|---|---|
| Direct molecular bonding | Plasma-activated wafer bonding of III-V epi to silicon | Mature | Excellent thermal/optical |
| Adhesive (BCB) bonding | Polymer adhesive layer between III-V and silicon | Mature | Good optical; moderate thermal |
| Solder bonding (AuSn, AuIn) | Eutectic metallization | Production-ready | Excellent thermal; coarse alignment |
| Micro-transfer printing | Polymer stamp picks up III-V chiplets and prints to silicon | Emerging | Good; very high throughput potential |
| Direct epitaxial growth | III-V grown on silicon via lattice-engineered buffers | Research | Variable; dislocations limit performance |
| Silver-epoxy bonding | Conductive epoxy bonds singulated laser die to silicon submount | Active research | Good thermal; suitable for prototypes and small-volume production |
Standard process flow for heterogeneous III–V-on-silicon:
- Fabricate silicon photonic wafer with passive structures (waveguides, MMI couplers, ring resonators, edge couplers, photodetectors) using standard CMOS-compatible processes
- Pattern recesses in the silicon photonic wafer where III–V will be placed
- Bond an unprocessed III-V wafer (containing the epi stack for laser active regions) to the silicon photonic wafer, face-down
- Remove the III-V substrate by selective etching, leaving only the thin epitaxial laser structure bonded to silicon
- Pattern III-V mesas, contacts, and metallization aligned to the underlying silicon waveguides
- Singulate and test
Optical coupling between III-V and silicon. The silicon waveguide and the III-V active region must transfer light between them efficiently. Standard approach: an adiabatic taper in the III-V mesa width gradually shifts the optical mode from being primarily in the III-V (where it sees gain) to primarily in the silicon (where it propagates with low loss). Typical adiabatic transition: 100 – 500 μm long, single-mode transition with dB loss.
Performance vs monolithic InP. Heterogeneously-integrated lasers on silicon now reach competitive performance:
- Threshold current: 10 – 30 mA (vs 5 – 15 mA for native InP)
- Side-mode suppression ratio: 40 – 50 dB
- Slope efficiency: 0.15 – 0.30 W/A
- Operation to 80 °C
- Bandwidth: 25 – 30 GHz directly-modulated
The cost advantage is the dominant motivation: heterogeneous integration on a CMOS-compatible silicon photonic substrate can leverage the same massive infrastructure that produced silicon ICs.
Future direction: monolithic III-V on silicon. Growing the III-V active region directly on silicon by epitaxy (rather than wafer-bonding) would simplify the process further. Quantum-dot lasers grown on silicon have demonstrated room-temperature CW operation and approach commercial viability. Threading-dislocation densities of cm remain a challenge versus cm in native InP.
References: Park et al., Heterogeneous Integration of Indium Phosphide-Based Photonic Integrated Circuits on Silicon Substrates, IEEE JSTQE 2020; Liang & Bowers, Recent progress in lasers on silicon, Nature Photonics 2010.