Process design kit (PDK)

A photonic integrated circuit made in a shared foundry is designed by people who never see the fab. The process design kit is the contract between them. It carries the process description (the layer stack, which mask layers exist, their thicknesses and etch depths), the design rules that a layout must satisfy (minimum widths, gaps, overlaps and densities, checked automatically by design-rule checking), and a library of components the foundry has already fabricated and measured: waveguides, bends, grating and edge couplers, splitters, phase shifters, modulators and germanium photodetectors.

Each library component comes with a fixed layout cell and, increasingly, a compact model: a frequency-domain description (S-parameters versus wavelength) or a behavioral model with a few parameters, such as insertion loss, effective and group index and their temperature coefficients, bandwidth and $V_\pi$. A circuit simulator chains these models to predict the response of the whole circuit before tape-out, in the way electronic designers simulate with transistor models. The models are measured on the foundry's own wafers, so they are statistics over a process rather than the performance of one best device, and good PDKs publish corner or variability data alongside the nominal values.

The value of a PDK is largely in what it lets a designer not do. Using a characterized coupler or detector avoids a design-and-fabrication cycle that can take months on a multi-project wafer run, and staying inside the rules avoids the manufacturing failures that the rules exist to prevent. The limits follow from the same fact: a PDK's components are general-purpose, and a design that needs a different waveguide geometry, a tighter spectral response, or an unusual wavelength band must build and characterize its own components, often as custom cells verified against the rules only.

Photonic PDKs are younger than their electronic counterparts and less uniform. Wavelength dependence, polarization and phase errors from nanometer-scale width variation have no direct electronic analogue, and the models for them are still maturing; so are the checks that layout matches schematic, since optical connections cannot be verified by the simple connectivity rules used for wires. The same foundries offer wafer-level test structures and procedures, and a PDK often defines the test couplers and pad layouts that let a chip be probed on the wafer.

References: L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University Press, 2015); W. Bogaerts and L. Chrostowski, Laser Photonics Rev. 12, 1700237 (2018).