Wafer-level test
Electrical and optical characterization of photonic or optoelectronic devices while they are still on the un-diced wafer, before any singulation or packaging. The dominant characterization mode in modern silicon photonic foundries.
Wafer-level test (sometimes called "wafer probe" or "wafer screening") is the practice of characterizing individual devices on a wafer before the wafer is diced into separate chips. Devices that fail the wafer-level screen are marked as "bad" and discarded after dicing; only devices that passed wafer-level test proceed to packaging.
Why wafer-level test is cheap. Packaging, and fiber attachment in particular, is one of the most expensive steps in making an optoelectronic module, and a device found to fail after packaging wastes that whole cost. Wafer-level test catches most failures before any packaging cost is spent.
Standard wafer-level test setup:
| Component | Function |
|---|---|
| Vacuum chuck stage with X/Y/θ stepping (sub-μm precision) | Position each die under the optical and electrical probes |
| Probe card with multiple electrical contacts | Apply bias, measure current/voltage, drive heaters |
| Optical input/output through grating couplers on the die | Fiber-coupled optical probes; vertical alignment to the chip surface |
| Tunable laser source + power meter | Optical characterization (transmission, loss, FSR) |
| Test execution system | Automates per-die measurements; logs results to wafer map |
Why grating couplers dominate wafer-level test. Edge couplers require polished facets, which means dicing the wafer, defeating the purpose of pre-dicing test. Grating couplers couple from the surface of the die at any position on the wafer, requiring only that a fiber tip be vertically aligned to the grating area. Modern silicon photonic foundry process design kits (AIM Photonics, IMEC iSiPP50G, GlobalFoundries 9WG) include grating couplers at standardized positions for automated wafer test.
Throughput. A typical silicon photonic wafer-level test station tests about one device every 5–30 seconds, depending on test complexity, so the time per wafer follows from the number of devices tested: 1,000 devices take 1.4 to 8.3 hours, and 10,000 take 14 hours to 3.5 days. A 200 mm wafer has room for only about 25 full reticle fields of 26 × 33 mm, but each field holds many dies and test structures, so the number of devices is chosen with the test time in mind.
What is tested at wafer level for silicon photonics:
- Grating coupler loss: verifies optical I/O works at all
- Insertion loss of passive structures (waveguide spirals, MMIs, directional couplers)
- Resonator FSR and Q: verifies microring designs
- Modulator and bandwidth (RF probes required)
- Photodetector dark current and responsivity
- Heater resistance: verifies thermal tuners
- DC continuity: verifies no shorts or opens in metal stack
What requires post-dicing (die-level) test:
- Edge coupler loss: needs polished facet
- Final yield against system-level specs: combines device-level results
- High-temperature reliability: wafer chuck is typically room-temperature
- High-power damage threshold: risk of damaging neighboring devices on wafer
Yield mapping. Wafer-level test results are logged with die coordinates, producing a 2D wafer map showing pass/fail and parameter distributions across the wafer. Spatial patterns (edge ring failures, center vs edge gradients, defective reticles) often indicate specific process problems and feed back into process control. In a mature process the map is mainly a screen; in a process still under development it is as much a tool for finding where dies are lost.
De-embedding the probes. Grating-coupler probes are wavelength- and polarization-selective, so the coupler's own spectrum must be removed from every device measurement, usually via back-to-back reference structures on the same die. Landing repeatability of a tenth of a decibel separates a usable loss map from noise, and temperature control matters because silicon's thermo-optic coefficient moves resonances tens of picometers per kelvin. Loss extraction itself leans on stepped test structures, spiral or ladder variants of the cutback method, stepped across every reticle so the fab can plot loss and index variation as wafer maps.
The co-packaged optics driver. Once a photonic die is bonded next to an expensive switch ASIC or buried in a multi-die module, a dead die is no longer a discarded chip but a discarded assembly, so known-good-die screening before assembly changes from good practice to a requirement, which is pulling RF and high-density optical probing deeper into foundry test flows.
Wafer-level test is one of the main cost advantages of silicon photonics over III–V photonics. Edge-emitting InP lasers with cleaved facets have to be cleaved into bars before they can be tested, while a silicon photonic wafer can be tested whole on a wafer chuck through its grating couplers.
The probe station, test flow and wafer maps are described step by step in Wafer-Level Optical Testing.
Where wafer-level test fits in a foundry shuttle run is described in Silicon Photonics Foundries, PDKs and MPW Runs.
References: L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University Press, 2015), chapter "Testing and packaging"; N. M. Fahrenkopf et al., "The AIM Photonics MPW: A Highly Accessible Cutting Edge Technology for Rapid Prototyping of Photonic Integrated Circuits," IEEE J. Sel. Top. Quantum Electron. 25 (2019).